// (C) Copyright 2012 Kystar. All rights reserved.

`timescale 1ns/100ps
`default_nettype none

module net_mac_addr 
(
    input  wire          I_sclk,
    input  wire          I_net_in_en,
    input  wire [  7: 0] I_net_in_data,
    output reg           O_net_out_en,
    output reg  [  7: 0] O_net_out_data,
    input  wire          I_reg_mac_addr_incr_en
);

/******************************************************************************
                                <localparams>
******************************************************************************/
localparam
    MAC_ADDR_OFFSET = 'd19;

/******************************************************************************
                              <internal signals>
******************************************************************************/
reg  [ 7: 0] cnt;
reg  [ 7: 0] mac_addr;

/******************************************************************************
                                <module body>
******************************************************************************/
always @(posedge I_sclk)
    if (I_net_in_en && !O_net_out_en)
        mac_addr <= mac_addr + 1'b1;

always @(posedge I_sclk)
    if (!I_net_in_en)
        cnt <= 'd0;
    else if (cnt != 8'hff)
        cnt <= cnt + 1'b1;

always @(posedge I_sclk)
    O_net_out_en <= I_net_in_en;
    
always @(posedge I_sclk)
    if (I_reg_mac_addr_incr_en)
        begin
        if (cnt == MAC_ADDR_OFFSET)
            O_net_out_data <= mac_addr;
        else
            O_net_out_data <= I_net_in_data;
        end
    else
        O_net_out_data <= I_net_in_data;

endmodule
`default_nettype wire

